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After that, I noticed that the reserved area has a specific start, and may not exactly end where the stolen memory ends. Put the '0x' in place. Note that there is also a GEN2 version of this register, but that's on a different address so not handled in this patch. Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_runtime_pm.c ee27921824e6ad0ca2d8e5abfa12cf4d853ded6c 08-Jul-2015 Ville Syrjälä drm/i915: Enable DPIO SUS clock gating on CHV CHV has supports some this content

Also GT perf freqency register is different for Broxton so update that. Signed-off-by: Jordan Justen Reviewed-by: Kristian Høgsberg Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_cmd_parser.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 022e4e52a750066047b22031733df70e136ae299 30-Sep-2015 Sunil Kamath drm/i915/bxt: Modify BXT BLC according to VBT changes Latest VBT mentions which Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_runtime_pm.c e0fce78f041014846d77940d3a350a4cffe4ab2b 08-Jul-2015 Ville Syrjälä drm/i915: Implement PHY lane power gating for CHV Powergate the PHY lanes There's also one extra complication I've not yet considered; Some of the DSPARB registers contain bits related to multiple pipes. https://www.vistax64.com/general-discussion/277042-sony-vaio-laptop-pll-found-yay.html

So add the code to decode it. v4: Squash uC-independent code into GuC-specifc loader [Daniel Vetter] Don't keep the driver working (by falling back to execlist mode) if GuC firmware loading fails [Daniel Vetter] v5: Clarify WOPCM-related #defines A bit of extra care is needed to reconstruct the initial state of the DISPLAY_PHY_CONTROL register since it can't be read safely. Hook it up.

  • The registers are double buffered but apparently they update on the vblank of any active pipe.
  • Another important detail in the DP code is the "TX latency optimal" setting.
  • This information is filled in intel_device_info and is available to user with GET_PARAM.
  • Signed-off-by: Ville Syrjälä Reviewed-by: Deepak S Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_runtime_pm.c 3e28878635cc3bb3159445dc9cfbdc3d34eb8daf 08-Jul-2015 Ville Syrjälä drm/i915: Force CL2 off in CHV x1 PHY We can choose to
  • Signed-off-by: Paulo Zanoni Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_gem_stolen.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 245d96670d2655f70f4445d5247f26afbe705c84 03-Aug-2015 Arun Siluvery drm/i915:skl: Add WaEnableGapsTsvCreditFix Cc: Ben Widawsky Cc: Joonas Lahtinen Signed-off-by:
  • drive port B with pipe B.
  • Making changes to handle this.
  • intel_enable_dsi_pll Wrapper function to use same code for multiple platforms.

So instead read the actual lane status from the DPLL/PHY_STATUS registers and use that to determine which lanes ought to be powergated initially. If root cause for system hang is found and can be worked around with another means, we can reconsider if we can reinstate full reset for unreadiness case. Normally the second TX lane acts as some kind of reset master, with the other lanes as slaves. This function programs the calculated clock values on the PLL. 3.

Signed-off-by: Ville Syrjälä Reviewed-by: Paulo Zanoni Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_irq.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h 74c0b395fce4c807a49c404fb59462b22069b001 27-Aug-2015 Ville Syrjälä drm/i915: Add port A HPD support for SPT On SKL the port Signed-off-by: Imre Deak Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_gpu_error.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h bd93a50e4dbae108a55a228bba1a69a2314096fb 30-Sep-2015 Imre Deak drm/i915: rename INSTDONE to GEN2_INSTDONE We have a bunch of INSTDONE registers To work around this we simply check for the 0 value of the CL2 register (which is what we get when it's powered down) and adjust our expectations. In this case we trick CL2 (where the DPLL lives) into life by temporaily powering up the lanes in the second channel, and once the pipe is up and runnign we

v2: Fix SPT and VLV. v4: - Code formatting. (Chris Wilson) - re-privatised mocs code. (Daniel Vetter) v5: - Changed the name of a function. (Chris Wilson) v6: - re-based - Added Mesa table entry (skylake But let's ignore that mess for now. This implementation uses MI_LOAD_REGISTER_MEM which is currently only used by command parser and was using a default length of 0.

Signed-off-by: Imre Deak Reviewed-by: Ben Widawsky Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_gpu_error.c /linux/stable/drivers/gpu/drm/i915/i915_reg.h f1d543485344f11f90e5fac637cc3430841ddabf 30-Sep-2015 Imre Deak drm/i915: remove duplicate names for the render ring INSTDONE register We use http://www.pocketables.com/forum/archive/index.php/t-2175.html v6: Rebased Issue: VIZ-4884 Signed-off-by: Alex Dai Signed-off-by: Dave Gordon Reviewed-by: Tom O'Rourke Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_guc_loader.c 33a732f407fed464df687370d7bb4d64533f9920 12-Aug-2015 Alex Dai drm/i915: GuC-specific firmware loader v4: Starting afresh and not modifying existing state for backlight, as per Jani's recommendation. Thanks to Clint for the VLV code.

After we merge the patch series that allows user space to allocate stolen memory we'll be able to write IGT tests that maybe catch the bugs fixed by this patch. http://elizabethandrew.org/sony-vaio/sony-vaio-ej3.html v3: Removed a redundant change wrt code comment. By trying to keep the registers consistent across the different engines it should make the programming for the registers consistent. v2: s/WARN_ON_ONCE/WARN_ON/ since it's in one time init code anyway (Paulo) Cc: Paulo Zanoni Cc: Chris Wilson Acked-by: Paulo Zanoni Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter

Making use of this field in BXT BLC implementation. We could proceed with reset anyway, but with some hangs with skl, the forced gpu reset will result in a system hang. At that point the power state of CL2 has somehow gotten entangled with the power state of the first channel. have a peek at these guys This support is to be added by follow-up patches.

If this is not the case, we fail. v9 (Francisco Jerez): - Minor style fixes. This patch may solve random stolen memory corruption/problems on almost all platforms.

Program 8by3 divider to generate Rx clock v2: Fixed Jani's review comments.

By inspecting the unreadiness for reset seems to correlate with the probable system hang. BXT modeset sequence needs vdisplay and hdisplay programmed for transcoder. 3. That means that if we check for the expetected power state immediately upon releasing cmnreset we would get the occasional false positive. PDP update in bb_start is only for legacy 32b mode.

So adding a new function to program following clocks and dividers: 1. BXT port control register is different than VLV. 2. v2: - Remove pointless VLV check (Ville). check my blog v2: Add missing ':' to the pipe config debug dump Signed-off-by: Ville Syrjälä Reviewed-by: Sivakumar Thulasimani Signed-off-by: Daniel Vetter /linux/stable/drivers/gpu/drm/i915/i915_reg.h /linux/stable/drivers/gpu/drm/i915/intel_ddi.c /linux/stable/drivers/gpu/drm/i915/intel_display.c /linux/stable/drivers/gpu/drm/i915/intel_dp.c /linux/stable/drivers/gpu/drm/i915/intel_dp_mst.c /linux/stable/drivers/gpu/drm/i915/intel_drv.h 2dba3239f5c7511ffac957887facd0a0c9d003a5 30-Jul-2015 Michel

v2: -'static const' for private data structures and style changes.(Matt Turner) v3: - Make the tables "slightly" more readable. (Damien Lespiau) - Updated tables fix performance regression. Simplified the logic for bit definitions for MIPI PORT A and PORT C in same registers. In this setup, userspace should only utilize the first N entries, higher entries are reserved for future use. Although the GEN4 version's layout is different, we treat it the same way as the GEN7+ version, in that we simply read it out during error capture.

Removed the changes in VLV/CHV code. v2: Rebased due to crtc->config changes s/HDMI_GC/HDMIUNIT_GC/ to match spec better Factor out intel_enable_hdmi_audio() Signed-off-by: Ville Syrjälä Reviewed-by: Ander Conselvan de Oliveira Reviewed-By: Chandra Konduru Testecase: igt/kms_render/* Signed-off-by: v3: Refactored the macros for TX, RX Escape and DPHY clocks as per Jani's suggestion. We will only proceed with reset if all engines report that they are ready for reset.

Introduce new register defines that contain information on slices on Broadwell. v3: Jani's review comments - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK - Disable UTIL_PIN if controller 1 is used - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling UTIL_PIN - check valid controller value Also, the registers are used in case control pin indicates display DDI. All registers in powered down blocks will reads as 0xffffffff, and soe we would drown in warnings from vlv_dpio_read() if we allowed the code to access all those registers.

So doing the FIFO reconfiguration properly when multiple pipes are active is not going to be fun. With potentially some lanes powered down, the DP code now has to check the number of active lanes before accessing PCS/TX registers. Main changes are: 1.